1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly to a fully hidden refresh DRAM (Dynamic Random Access Memory) capable of fully hiding a refresh operation internally executed from an outside. More specifically, the present invention relates to a dynamic type semiconductor memory device having an interface compatible with an SRAM (Static Random Access Memory).
2. Description of the Background Art
In a DRAM (Dynamic Random Access Memory), generally, a single memory cell is constructed by one transistor and one capacitor. The area occupied by the memory cell is therefore small and the DRAM is suitable to implement a memory device of a large storage capacity. However, the DRAM stores information in the form of electric charges in a capacitor. With elapse of time, therefore, the electric charges accumulated in the capacitor leak out and data is lost. To prevent data from being lost due to the leakage of the electric charges, a refreshing operation of periodically rewriting stored data must be executed. In a normal operation mode for performing a data access, an external memory controller controls a timing of executing the refreshing.
On the other hand, in an SRAM (Static Random Access Memory), a single memory cell is constructed by four transistors and two load elements, and the area occupied by the memory cell is larger as compared with a DRAM cell. However, the SRAM cell is basically constructed by a flip flop and stores data as long as the power is supplied, so that refreshing of data does not need to be executed. Therefore, generally in portable equipment or the like, an SRAM is used as a main memory from a viewpoint of controllability.
Also in the field of portable equipment or the like, as the functionality is enhanced, it is demanded to handle a large amount of data such as image data and audio data and to increase the storage capacity of a main memory device sufficiently. In the case of constructing such a memory device of a large storage capacity by an SRAM, the occupied area becomes large, and it greatly hinders reduction in the size of the whole system.
A hidden refresh DRAM requiring no external refresh control is being proposed as a main memory device of a large storage capacity as an substitution of an SRAM. In such a hidden refresh DRAM, a refresh request is issued internally at predetermined intervals and a refreshing operation is executed internally in accordance with the refresh request. When a data access from an outside and the internal refresh request conflict with each other, the operation designated earlier is executed by an arbitration circuit. For example, when a refresh request is supplied at a timing faster than instruction of a data access (data writing or data reading), first, the refresh operation is executed. After completion of the refreshing operation, the data access operation is executed in accordance with the data access instruction from the outside.
The hidden refresh DRAM which does not require an external controller to control a refresh is called a fully hidden refresh DRAM or a VSRAM (Virtual Static RAM). An example of such a memory is disclosed by Sawada et al., xe2x80x9cA 30 xcexcA Data-Retention Pseudostatic RAM with Virtually Static RAM Modexe2x80x9d, IEEE, Journal of Solid State Circuits, Vol. 23, No. 1, pp. 12 to 17.
In a fully hidden refresh DRAM completely hiding a refresh operation from an outside and requiring no external refresh control, a refresh request is issued by using a built-in timer circuit (refresh timer) at predetermined time intervals. In response to the refresh request, a refresh is executed in accordance with an internally generated refresh address. The refresh timer operates asynchronously with an external data access. When the data access instruction from the outside and the refresh request conflict with each other, data is destructed. It is therefore necessary to arbitrate between the refresh request and the data access request as described above.
In the above-mentioned prior art document, a flip flop is employed, as such an arbitration circuit, to receive both a normal access request generated by a chip enable signal /CE and an internally generated refresh request, and determines which one of the requests is activated faster. As a determination circuit, in the prior art document, an NAND type flip flop is used. Therefore, to successively execute a refresh and a data access when the refresh request and the data access request conflict with each other, even when a signal indicative of one of the requests becomes inactive, it is necessary to maintain the other signal in an active state. Thus, a refresh request activation period becomes longer than a period in which the refresh is executed internally, and the activation period of the data access request signal also has to be set to be longer than the period required for completion of the refreshing operation. Consequently, for example, a command instructing a data access cannot be applied in the form of a one-shot pulse synchronously with a clock signal, as an externally applied data access instruction.
In the prior art document described above, the data access request is activated according to chip enable signal /CE. Therefore, such a problem occurs that the prior art technique cannot be applied to an interface using an address transition detection signal which is commonly widely used in an interface of an SRAM. Specifically, in the document, chip enable signal /CE has to be toggled in accordance with a data access. It is impossible to change an address signal to define a memory cycle by the change in address signal under a state where chip enable signal /CE is fixed at an L level. Therefore, the prior art device cannot accommodate for an address transition detection type interface, and a DRAM having complete compatibility with an SRAM cannot be implemented.
In a case where successive data accesses are performed, in the configuration of the prior art document, the data accesses are accepted continuously. In the technique of the prior art document, a word line is automatically driven to an inactive state after elapse of a predetermined time. However, in the case where the next data access instruction is supplied before the predetermined time elapses, a data access operation is performed before internal circuitry reliably returns to a precharge state, so that a data collision occurs. A problem such that an accurate data access cannot be ensured arises.
A selected word line is maintained in an active state for a predetermined time. Therefore, operation of selecting a row and a column has to be performed in each access cycle. In a DRAM, since data is read destructively, it is required to perform a column selection after the row selecting operation is performed and data of a memory cell is sensed and latched by a sense amplifier and latched. Therefore, it is difficult to successively access different columns under the state where a word line is maintained in a selected state, as in a page mode. A problem such that the high speed access mode cannot be achieved arises.
In the case of detecting a transition in address signal and defining a memory cycle, a countermeasure against noise in an address signal has to be taken. However, since a conventional fully hidden refresh DRAM does not use an address transition detection signal, the problem of noise in the address transition detection signal is not considered.
An object of the present invention is to provide a DRAM based semiconductor memory device having full compatibility with an SRAM interface.
Another object of the present invention is to provide a fully hidden refresh type DRAM having an address transition detection type interface.
Still another object of the present invention is to provide a fully hidden refresh type DRAM having an address transition detection type interface which operates reliably without being influenced by noise of an address signal.
Yet another object of the present invention is to provide a fully hidden refresh type DRAM capable of operating in a high-speed access mode.
A semiconductor memory device according to a first aspect of the present invention includes: a plurality of memory cells; an operation mode instruction signal generating circuit for generating an operation mode instruction signal; a cell selection control signal generating circuit for generating a cell selection control signal in response to the operation mode instruction signal; a delay circuit for delaying the cell selection control signal; a cell selection activation control signal generating circuit for generating a cell selection activation control signal for controlling an operation of selecting the plurality of memory cells in response to an output signal of the delay circuit; and a mask circuit for prohibiting transfer of the operation mode instruction signal to the cell selection control signal generating circuit in response to the cell selection control signal.
A semiconductor memory device according to a second aspect of the present invention includes: a plurality of memory cells arranged in rows and columns; row address transition detection circuit for detecting a transition in row address signal designating a row of the memory cells and generating a row address transition detection signal; a column address transition detection circuit for detecting a transition in column address signal designating a column of the memory cells and generating a column address transition detection signal; an array activating signal generating circuit for generating an array activating signal for activating/inactivating the memory cell selecting operation in response to the row address transition detection signal; and a column selection control signal generating circuit for generating a column selection activating signal for activating an operation of selecting a column of the memory cells in response to activation of either the array activating signal or the column address transition detection signal.
A semiconductor memory device according to a third aspect of the present invention includes: a plurality of memory cells; an address transition detection circuit for detecting a transition in address signal designating an address of a memory cell in the plurality of memory cells and generating a one-shot address transition detection signal; a pulse width change circuit for changing a pulse width of the address transition detection signal; and a cell selection control signal generating circuit for generating a cell selection control signal for controlling the memory cell selecting operation in response to an output signal of the pulse width change circuit.
By selectively transferring an operation mode instruction signal in accordance with a cell selection control signal to an operation mode instruction signal generating circuit, conflict between a state of the cell selection control signal and a change of a state of the cell selection control signal according to an operation mode instructed by the operation mode instruction signal can be prevented internally. Thus, the internal operation can be executed accurately.
Particularly, in the case of utilizing the address transition detection signal as the operation mode instruction signal, the internal operation reset and the internal operation activating instruction are designated by the leading and trailing edges of the address transition detection signal, respectively, so that activation of the internal operation and inactivation of the internal operation can be prevented from being simultaneously designated. Thus, a semiconductor memory device, operating accurately and having an address transition detection type interface compatible with an SRAM interface, can be implemented.
By utilizing a row address transition detection signal for controlling row selection and a column address transition detection signal for controlling column selection, different column addresses can be successively accessed under a state where a row is maintained in a selected state. Therefore, a high-speed access mode can be implemented in the semiconductor memory device having an address transition detection type interface.
By changing the pulse width of the address transition detection signal, even if the address transition detection signal is insufficient due to noise in an address signal, a pulse signal of a sufficient pulse width can be generated. Thus, a semiconductor memory device having an address transition detection type interface having a large margin against noise in an address signal can be implemented.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.